In general, there are two types of reset in a computer system, namely, a cold reset and a warm reset. To cold reset a computer system is to power down substantially all or all of the computer system and then to restart the computer system. In contrast, to warm reset the computer system is to restart the computer system, which is already turned on, via the operating system of the computer system. During the warm reset, the power in the computer system remains substantially stable. A user or a software application running on the computer system may initiate the warm reset.
Currently, many memory devices do not support an input control that permits an asynchronous logic reset to put the memory devices into a known initial logic state. To reach a known initial logic state for proper operation in the memory devices, a power cycling sequence is performed to initialize the memory devices. In other words, the memory devices go through a sequence of powering off and then on in order to be properly initialized to a known logic state, which is also referred to as a known state.
While running a power cycling sequence in the memory devices does not significantly impact the computer system when the computer system is powered up from a cold state, the power cycling sequence should not be run when the computer system is to be reset from a warm state because by definition a power cycling sequence is not a warm reset. As a result of no power cycling sequence when coming out of a warm reset, the memory devices will start with whatever state the memory devices were in previously before the warm reset. If the previous state is a known initial state, then the warm reset does not create a problem. However, if the previous state is an arbitrary unknown state, then the system cannot boot up because the memory devices are in the arbitrary unknown memory state after the warm reset.
In a prior art memory controller, also commonly referred to as a memory controller hub (MCH), the MCH is reset asynchronously in response to a system warm reset. The asynchronous reset of the MCH results in a non-deterministic timing relationship of interfacing signals (e.g., RAS#, CAS#, WE#, CKE controls, and CK/CKB clocks) between the MCH and the memory devices. This non-deterministic timing relationship may violate the setup and hold timing requirements of the interfacing signals relative to the clock signals of the memory devices. Furthermore, such a violation may cause the memory devices to enter into one or more arbitrary unknown states. To recover from the unknown states, the memory devices have to go through a power cycling sequence after the asynchronous reset.
However, it is problematic to force the memory devices to go through a power cycling sequence as this action by definition is a cold reset, as opposed to the intended warm reset.